Tuned plated wire content addressable memory

ABSTRACT

A wire element is electrically tuned so that it operates with a low impedance. Bit information is then readily transferred along the wire from one location (sender) to another location (receiver) by energizing the drive strap adjacent the sending bit with a burst of pulses. When the circulating current in the wire builds up to a maximum value, the drive strap adjacent to the receiver bit is energized with a single pulse. The receiver bit will then switch if its binary state is opposite to that of the bit at the transmitter.

United States Patent [72] Inventor William J. Bartik Wyncote, Pa.

[21] Ap l. No. 712,108

[22] Filed Mar. 11, 1968 [45] Patented May 25, 1971 [73] Assignee SperryRand Corporation New York, N.Y.

[54] TUNED PLATED WIRE CONTENT ADDRESSABLE MEMORY 4 Claims, 2 DrawingFigs. [52] US. Cl 340/174 [51] Gllc 11/14, G1 1c 15/00 [50] Field ofSearch 340/174 (TF); 307/88 (P) [55] References Cited UNITED STATESPATENTS 3,482,223 12/1969 Spandorfer et a1. 340/174 3,413,485 11/1968Oshima 307/88 3,440,436 4/1969 Oshima et al. 307/88 3,399,309 4/1968Bartik et al. 307/88 3,296,453 1/1967 Ghisler 307/88 ,295 6/1967Proebster 340/174 3,371,326 2/1968 Fedde 340/174 3,421,153 1/1969 Bartiket al. 340/174 OTHER REFERENCES Publication 1. IEEE Transactions onElectronic Computors Vol. EC-16 No. 5 Oct. 1967, pgs 642- 652 PrimaryExaminer-James W. Moffitt Attorneys-Charles C. English, Rene A. Kuypersand William E. Cleaver PATENIEUHAYZSIQYI 3581.294

' DRIVER AND TIMING CIRCUITS Fig. I

TRANSMITTING STRAP CURRENT OUTPUT VOLTAGE OIF WIRE E /B OUTPUT FOR AsToRED "I" CURRENT (c) I IN WIRE DuTPuT FOR A sToRED "o" RECEIVING STRAP(d) CURRENT INVENTOIR WILL/AM J. BART/K ATTORNEY TUNED PLATED WIRECONTENT ADDRESSABLE v MEMORY The instant application is related toapplications having Ser. Nos. 466,904, now U.S. Pat. No. 3,487,380,475,94I now U.S. Pat. No. 3,449,731 and 499,971 now U.S. Pat. No.3,460,] I4 by Woo F. Chow and Ser. No. 67l,645, now U.S. Pat. No.3,524,174 by Carlos F. Chong.

This invention relates in general to memory devices and in particular toplated wire memory devices for use in content addressable memories.

One of the difficulties encountered in transferring information along asmall diameter plated wire memory device has been that the impedance ofthe latter is relatively high. The prior art techniques have involvedusing mechanical expedients to lower the plated wire impedance. Thesetechniques involve essentially making the plated wire into a coaxialline. In view of the small size of the wire and the difficulty informing this wire into a coaxial line, the prior artmechanicalarrangements have not been entirely satisfactory.

In summary, this invention relates to an arrangement for reducingtheimpedance of a plated wire memory element, which is primarilyinductive, by tuning out the latter with a capacitor. This arrangementenables the wire memory to operate in a relatively low impedance mode.Information is readily transferred along the wire from one bit positionto another bit location by first applying a burst of square waves to thesender strap (i.e., transmitter) located adjacent one bit ofinformation. When the current in the wire has builtup to a maximum, thereceiver drive strap which is juxtaposed to a second bit location isenergized with a single pulse. If the information adjacent the senderstrap is different from the information adjacent the receiver strap, theinformation in the later is switched. In the event that the bitinformation at the sender locationis identical to the receiver location,there will be no switching of information. Accordingly, information canbe readily transferred from one location to another location along theplated wire.

Accordingly, it is an object of this invention to provide a new andimproved arrangement of a content addressable memory using plated wirememory elements.

It is a further object of this invention to provide for a new andimproved plated wire content addressable memory which will allow foreasier mechanical construction.

It is yet a further object of this invention to provide for a new andimproved plated wire content addressable memory which will enable longerplated wires and larger work lengths to be employed.

Referring now to the drawings, FIG. I depicts an exemplary device whichutilizes the instant invention.

FIG. 2 further depicts the various signals applied to the device in FIG.1.

Referring now to FIG. 1 in greater detail, plated wires I and 12 areplated magnetizable wires which comprise 5 mil beryllium coppersubstrates upon which is coated a Permalloy film. The Permalloy film isdeposited with a thickness of approximately 10,000A and is depositedwith the property of uniaxial anisotropy. The property provides an EASYaxis which is circumferential to the wire and a HARD axis which is alongthe length of the wire.

Connected in series with the respective plated wires I0 and 12 are thecapacitors l8 and 20. The capacitors I8 and 20 are tuning capacitors andare selected to tune out the inductance of the wires 10 and I2. In otherwords, the impedance to current in the wires 10 and I2 is primarilyinductive and the tuning capacitors 18 and 20 eliminate the effect ofthis inductance. Therefore, the current in the wire is limited only bythe resistance. One feet of wire would have approximately 1.5 ohms ofthe resistance.

Arranged orthogonally to wires 10 and 12 are the drive straps l4 and 16.The width of the straps l4 and I6 is determined by the amount of currentthat is to be generated in the plated wires 10 and 12. In other words,the amount of magnetic material underneath the straps l4 and I6 that isswitched when the respective straps are energized determines the amountof current that will be induced in the plated wires. This aspect will bediscussed in greater detail below. The drive straps I4 and 16 are shownconnected to the driver'and timing circuit block 11. In the exemplaryembodiment of FIG. 1, the drive strap 14 is connected to a multipulsegenerator source whereas the energizing means connected to the drivestrap 16 is a single pulse generating source. As will be explained ingreater detail with respect to FIG. 2, the respective energizing meansapplied to straps l4 and 16 are applied at different times and hence atiming circuit is also required and is included within block 11. Sincethe driver'energizing source and the timing circuit 1 I are well knownin the art, they will not be further discussed.

At the intersection of the respective drive straps I4 and 16 and theplated wires 10 and 12 there is stored binary information (i.e., a 0" ora I"). Whether a binary 0" or I is stored at the intersection of theplated wire and the drive strap is determined by the orientation of themagnetization vectors. In other words, a clockwise orientation of themagnetization vectors (as viewed from the right end of the wire lookingtoward the left) may represent a binary l and a counterclockwiseorientation of the magnetization vectors may represent a binary 0".Thus, at intersections 22 and 24, respectively, a l is stored (asrepresented by the clockwise vectors l5 and I9).

Information is transferred along the plated wires 10 and I2, that is,from location 22 to location 24 and from location 23 to location 25 inthe following manner. It is to be understood that other plated wirearrangements may be utilized for this transfer and FIG. I is merelyexemplary. For example, a reference strap may be utilized with thetransmitter strap in order to supply one-half of the current. Totransfer information from location 22 to location 24, a burst of pulsesshown in FIG. 2a is first applied to the drive strap 14 by means of thedriver and timing circuits 11. The application of the burst of pulses tothe transmitter drive strap 14 causes the magnetization vector 15 tooscillate to the position shown by the vector 15a and back again to itsquiescent point. This oscillation back and forth includes a voltage inthe plated wire 10 which approximates a sine wave as shown in FIG. 2b.The output voltage induced in the plated wire generates an oscillatorycirculating current in the plated wire 10 whose polarity depends onwhether a 1" or 0" is stored (see FIG. 20). When the frequency of thepulses in a burst corresponds to the resonant frequency of the platedwire, the circulating current builds up to a value which is limited onlyby the DC resistance of the plated wire. When the circulating currenthas built up to its maximum value, the receiver strap 16 is energizedwith a single pulse as shown in FIG. 2d. The circulating current in thewire will cause the receiver strap 16 to switch the information atlocation 24 if its binary state is different from the binary informationat location 22. This is accomplished in the following manner.

The solid output line in FIG. 2c represents the output cur rent for thebinary I stored at location 22. The single pulse (FIG. 2d) applied todrive strap 16 occurs during the half cycles, A-B and EC (FIG. 20). Thissingle current pulse causes the magnetization vectors 19 at location 24to rotate to the position 19a, which is some angle less than The currentgenerated during the half-cycle AB is positive and flows from the rightend to the left end in plated wire 10. This positive current is asteering current and causes the magnetization vector at position 19a tobe tipped back to the quiescent position shown by the vector 19. Inother words, since the transmitter information is a binary l and thereceiver information is a l there is no switching of the information andtherefore, in essence, the 1" at location 22 has been transferred tolocation 24.

Referring now to plated wire 12, the 0" information at location 23 willbe transmitted to location 5 in the following manner. The burst ofsignals shown in FIG. 2a is again applied to the transmitter strap 14 bythe driver and timing circuits II. This causes a voltage to be inducedin :plated wire 12 which is 180 out of phase with that shown in FIG. 2b.Accordingly, the current in the wire is oscillatory and is shown by thedotted wave forms shown in FIG. 2c. This oscillatory current flows in apositive and negative direction as shown. When the frequency of thepulses correspond to the resonant frequency of the word loop, thecirculating current shown depicted FIG. 2c builds up to a maximum value.When this maximum value occurs, the drive strap or receiver strap 16 isenergized by the driver and timing circuits 1 1 during a period shown inFIG. 2d. By applying the single pulse to strap 16 the magnetizationvector 21 rotates to the position 21a (the position less than 90); Thecurrent produced during the halfcycle E-C (FIG. 2c) will produce thenegative going signal which flows from the left to the right in platedwire '12. This steering current will tip the magnetization vector 21a tothe position 21b. in other words, the transmitter strap 14 hastransferred the information at location 23 to the receiver location 25by switching the binary l into a binary 0.

As was previously discussed, the capacitor connected to the plated wiretunes out the inductance and the current is limited only by theresistance. Thus, for a 35 milliampere steering current down one foot ofwire, which has a 1.5 ohm resistance, we need 52 millivolts from onestrap. Since 35 mils of strap gives about millivolts, about 175 mils ofstrap width are required of one transmitting strap supplies all of thecurrent. If the transmitting strap supplies one-half of the current withthe other one-half being supplied by a reference strap, a strap width of87.5 mils is required. It should be noted that the number of pulses inthe burst and the frequency of the burst are dependent upon thecharacteristics of the plated wire capacitor resonant circuit. Theresonant frequency of the plated wire circuit is where L is theinductance of the plated wire and C is the value of the capacitor in theword loop. Therefore, the frequency of the burst should correspond tothe resonant frequency of the word loop.

lclaim:

l. A memory arrangement comprising, a wire substrate having aferromagnetic coating deposited thereon for storing binary information,said coating being deposited with an EASY axis of magnetization which iscircumferentially oriented, means coupled to either end of saidsubstrate for electrically tuning said memory, said wire being therebyoperated in a low impedance mode, at least first and second juxtaposedconductors positioned substantially orthogonal to said wire substrate,the intersection of said first conductor and said memory comprising afirst information bit and the intersection of said second conductor andsaid memory comprising a second information bit, said first conductorbeing energized with a burst of pulses and said second conductor beingenergized with a single pulse, information being thereby transferredfrom said first bit location to said second bit location during theapplication of said single pulse.

2. The memory arrangement in accordance with claim 1 wherein saidinformation transfers from said first bit location to said second bitlocation is accomplished nondestructively.

3. The memory arrangement in accordance with claim 1 wherein timingmeans are coupled to said first and second conductors for energizing thelatter at different time periods, said second conductor being energizedat a time that corresponds approximately to the development of themaximum current in said wire.

4. The memory arrangement in accordance with claim 3 wherein binaryinformation is transferred by causing the rise time of the highest cycleof the current train of a first phase developed in said wire tocorrespond in time to said single pulse applied to said second strap andin the alternative, causing the fall time of the highest cycle of thecurrent train of a second phase developed in said wire to correspond intime to said single pulse applied to said second strap.

1. A memory arrangement comprising, a wire substrate having aferromagnetic coating deposited thereon for storing binary information,said coating being deposited with an EASY axis of magnetization which iscircumferentially oriented, means coupled to either end of saidsubstrate for electrically tuning said memory, said wire being therebyoperated in a low impedance mode, at least first and second juxtaposedconductors positioned substantially orthogonal to said wire substrate,the intersection of said first conductor and said memory comprising afirst information bit and the intersection of said second conductor andsaid memory comprising a second information bit, said first conductorbeing energized with a burst of pulses and said second conductor beingenergized with a single pulse, information being thereby transferredfrom said first bit location to said second bit location during theapplication of said single pulse.
 2. The memory arrangement inaccordance with claim 1 wherein said information transfers from saidfirst bit location to said second bit location is accomplishednondestructively.
 3. The memory arrangement in accordance with claim 1wherein timing means are coupled to said first and second conductors forenergizing the latter at different time periods, said second conductorbeing energized at a time that corresponds approximately to thedevelopment of the maximum current in said wire.
 4. The memoryarrangement in accordance with claim 3 wherein binary information istransferred by causing the rise time of the highest cycle of the currenttrain of a first phase developed in said wire to correspond in time tosaid single pulse applied to said second strap and in the alternative,causing the fall time of the highest cycle of the current train of asecond phase developed in said wire to correspond in time to said singlepulse applied to said second strap.